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VLSI Design of Low Power Fault Detection in SRAM using BIST

Tamilselvi M, Vedhanayagi P, Ramasamy K

Static Random Access Memory (SRAM) has become a key factor in new modern VLSI systems. Memories become more vulnerable to faults when the complexity of these memories increase as the technology shrinks. This detection of faults in SRAM has been a time consuming process. Hence transient current testing methods are used. This paper implements a transient current testing method to detect faults in Complementary MOSFET (CMOS) SRAM cells. By monitoring a transient current pulse during a write operation or a read operation, faults can be detected. In order to detect the fault, a Built in self-test (BIST) circuit is developed. Simulations are carried out on a 13T SRAM circuit, to detect the difference in waveform. To minimize the testing power in 13T SRAM were designed using transmission gates. It can be simulated using 0.25 μm CMOS process technology and also compared their simulation results with 6T SRAM cell. These qualities of the proposed design make it for high performance memory chips in the semiconductor industries