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Testing of AMBA Compliant Memory Controller using Pattern Generator/ Logic Analyser

Shilpa Rao, Arati.S.Phadke

With the growing imbalance between processor and memory performance it becomes more and more important to optimize the memory controller features to obtain the maximum possible performance out of the memory subsystem. As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. Improvements in memory latency and bandwidth have not kept pace with reductions in execution time of the instruction. Caches have been used extensively to compensate this mismatch, but some applications do not use caches effectively. As a result, the memory access time has been a hurdle which limits the performance of the system. The problem can be handled by designing a Memory Controller. This paper revolves around implementing and testing the Advanced Microcontroller Bus Architecture (AMBA) compliant Memory Controller as an Advanced Highperformance Bus (AHB) slave. The whole design is captured using Verilog, configured to a FPGA target device belonging to the Spartan 3A and Spartan 3AN family using Xilinx compiler, and simulated with ModelSim. The resulting bit file after compiling is then downloaded to a TKB3S board. The FPGA board is connected to the ADM’s LG320/LGLITE Integrated Logic Analyser and Pattern Generator for testing and verifying the design.