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Systolic Filter Design Using Multi-Filtering Techniques

Deepan Raj.B, T.V.P.Sundararajan, K.Shoukath Ali

To improve the performance of system in terms of processing power, a new architecture and clocking technique is to be realized in this paper. To process the signal in Embedded Parallel Systolic Filters (EPSF) and to eliminate the noise present in the signal using flag-bit and flicker clock condition. Kalman filter and extended kalman filter are the filtering techniques used by systolic arrays that can simultaneously triggered on all data elements with different clock cycles. Kalman filter and extended kalman filter to work in two conditions namely with and without flag-bit, flicker clock are to be synthesized and compared.