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SDR Implementation of Convolutional Encoder and Viterbi Decoder

Dr. Rajesh Khanna, Abhishek Aggarwal

This paper represents the SDR implementation of convolutional encoder and Viterbi decoder. In this paper there are two parts where one part is based on the VHDL simulation of encoder and decoder and second part is based on hardware, in which all these simulations are implemented on SDR (an FPGA). This paper has taken random bits as input bits to the transmitter. Convolutional encoder of ½ has been used in this paper. This paper uses the AWGN channel for analysis and different roll-off factors for RRC filter are also used. The motive of the paper is to analyze the bit error rate for different roll-off factors and to analyze the VHDL simulation with real time implementation on SDR.