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Resource Efficient Reconfigurable Processor for DSP Applications

P.C.Franklin, M.Ramya

Reconfigurable processor will configure the architecture based on the application. In general processor consists of data path, control and memory unit. In proposed system CSLA(Carry Select Adder) with BEC(Binary to Excess Converter) and CSLA with DLatch along with Wallace tree multiplier were developed to enhance the performance of MAC(Multiplication and Accumulation) in data path unit. Wallace tree multiplier and CSLA are used to reduce the size of the MAC unit. Multiplication and addition performed in MAC operation which can be enhanced for FIR(Finite Impulse Response) filters application. In MAC operation 16-bit CSLA with BEC and CSLA with D-latch architectures along with 8- bit Wallace tree multiplier which effectively reduces resource utilization. To make the function faster Wallace tree is replaced by Dadda tree multiplier. Reconfiguration in control unit also done for various functions using CSLA with Dadda tree multiplier. Control unit is designed for controlling the operations of the data path unit. By changing the data path and control unit architecture, resource utilization, power, delay and interconnects are reduced efficiently which mostly supports multimedia and DSP applications.