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Multi Threshold Low Power SRAM Using Floating Gates

Sushree Sangita Das, Kanan Bala Ray, Prangya Parimita Nanda

We investigate the mechanism of threshold voltage shifting of SRAM based on floating gates. Multi threshold SRAM based on floating gates is represented in this paper to reduce the power consumption and leakage current. By using multi threshold technique in SRAM based on floating gates, it consumes 66.39% less power for write'1' operation, 56.21% less power for write'0' operation, 23.35% less power for read'1' operation and 34.66% less power for read'0' operation as compared to SRAM using floating gates. It also consumes 90% less leakage current in hold state as compared to SRAM using floating gates in 180nM technology. For minimizing power consumption and leakage current, the concept of multi threshold is included in this paper.