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Low Power Phase Locked Loop Design with Minimum Jitter

Krishna B. Makwana, Prof. Naresh Patel

This paper describes a design of phase locked loop system with low power and minimum jitter. PLLs with high speed, low noise and wide bandwidth with fast acquistion time are preferred. A PFD with low dead zone, charge pump with passive low pass filter and a low noise, wide tuning VCO are integrated in the PLL system. A Telescopic OTA based VCO with wide tuning range of 450MHz to 1.9GHz and power consumption of 0.30mW is designed.. The PFD modeled is using 15 transistor and conventional charge pump with second order loop filter is used. Integrating this VCO in a PLL system offers low jitter and wide bandwidth. The results prove that maximum pull-in time is 150ns and the power consumed by this PLL system is 606uW at 1.5GHz.Measured jitter is 30ps in this PLL.