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Implementation of Single Cycle Access Structure for Logic Test

Prasana P, Viswanathan B

In this paper proposes a new single cycle access test structure for logic test. It will eliminates the unnecessary dynamic power consumption problem of conventional shift-based scan chains during switching transition in the scan FF and also reduces the accessing time into one clock cycles. This leads to more realistic circuit behavior during stuck-at and at-speed tests. And finally we developed BIST in vedic multiplier design where initially we developed new algorithm with normal FF and we replace by scan FF to prove the single cycle access. In testing mode the LFSR module will be used as a random generator for BIST application and in functional mode we will get multiplication operation. The structure allows an additional on-chip debugging signal visibility for each register.