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Implementation of a Low Power Carry Look Ahead Adder Using Adiabetic Logic

Debika Chaudhuri, Atanu Nag, Sukanta Bose

Now–a-days in digital circuit some important issues like high speed, high throughput, small silicon area, and low power consumption is being considered by designers. Full adders are important components in applications such as subtraction, counting, multiplication, filtering, digital signal processors (DSP) architectures and microprocessors. So for designer it is a great interest to design Carry-look ahead adder because of its high speed operation. In this paper power consumption and delay of a 4-bit carry look ahead adder, implemented in static CMOS and adiabetic logic (ECRL) is analyzed.