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FPGA Implementation of Image Compression Using SPIHT Algorithm

Mr.Vipin V, Miranda Mathews

A VLSI architecture designed to perform real time image compression using SPIHT with arithmetic coder is described here. The main advantage of SPIHT is that it is fully progressive and provide higher PSNR. SPIHT without list is proposed in this paper and which uses breadth first search method. BFS method is suitable for VLSI implementation. In order to archive more performance a high speed arithmetic coder architecture designed with SPIHT. Matlab simulation is used for verifying the result.