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FPGA Implementation of 3/6 SRFFT Algorithm for Length 6*m DFTS

M. Sathya, M.B.Annadurai

The Fast Fourier Transform (FFT) requires high Computational power, ability to choose the algorithm and architecture to implement it. This project explains the realization of a 3/6 FFT processor based on a pipeline architecture. The implementation has been made on a Field Programmable Gate Array (FPGA) as a way of obtaining high performance at economical price and a short time of realization. FPGA can be used with segmented arithmetic of any level of pipeline in order to speed up the operating frequency. The processor has been simulated up to 200 MHz, with an Xilinx Spartan 3E as a target device, for a transform length of 6 complex points. To combine the higher parallelism of the 6-FFTs and the possibility of processing sequences having length of any power of 6.The simultaneous operation of multipliers and adder-subtracters implicit in the 3/6 FFT, leads to faster operation at the same degree of pipeline. The 3/6 FFT algorithm is implemented in Xilinx FPGA Spartan 3E.