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Error Reduction in WiMAX Deinterleaver Address Generator by Using Majority Logic Circuit

A.Nandhini, D.Poornima Devi

A low-complexity and novel technique is proposed to efficiently implement the address generation circuitry of the 2-D deinterleaver used in the WiMAX transreceiver using the Xilinx field-programmable gate array (FPGA).The use of an internal multiplier of FPGA and the sharing of resources for quadrature phase-shift keying, 16-quadratureamplitude modulation (QAM), and 64-QAM modulations along with all possible code rates makes our approach to be novel and highly efficient when compared with conventional look-up table-based approach. We propose majority logic circuit for interleaver structure to reduce hardware complexity and error rate in WiMAX system. We also propose biorthogonal decoding to improve the hardware utilization efficiently. The proposed approach exhibits significant improvement in the use of FPGA resources. Exhaustive simulation has been carried out to claim supremacy of our proposed work.