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Energy Aware Optimized Resource Allocation Using Buffer Based Data Flow In MPSOC Architecture

Achyut karthikeya.T.G,Gowtham.M,Gautam.R,Selva kumar ,Janakiraman.N

This project presents a methodology for reducing interconnect resources in reconfigurable platforms for communication between processing units such as FPGA(Field Programmable Gate Array), MPSoC(Multiple Processor System On Chip) and NoC(Network-On-Chip). The evaluation of NoC architectures are NP-complete problem in the design of MPSoC. This proposed methodology implements the buffer based data flow architecture to reduce the overall design time and increase reconfigurability using dynamic virtual channel allocation. In this architecture the memory and bus allocation is shared to achieve high dynamic energy consumption and low interconnectresource utilization. The energy requirement for memory and bus allocation is continuously monitored and controlled within certain limit. This entire architecture is implemented in Xilinx 12.2 System Edition Software and realized in Xilinx Virtex 5 XUP FPGA kit. This proposed methodology expects the better optimization results in terms of energy compare to previous work. The mathematical representation of proposed work can be done using DAG (Data Acyclic Graph) and CDFG (Control Data Flow Graph) methods.