சுருக்கம்

Encoder And Decoder For (15,11,3) and (63,39,4) Binary BCH Code With Multiple Error Correction

R.Elumalai, A.Ramachandran, J.V.Alamelu, Vibha B Raj

In the present Digital Communication systems, it is highly possible that the data or message get corrupted during transmission and reception through a noisy channel medium. To get the error free communication we need Error correction code. BCH codes invented in 1960s are powerful class of multiple error correction codes with well defined mathematical properties, used to correct multiple random error patterns. The mathematical properties within which BCH codes are defined are the Galois Field or Finite Field Theory. The project proposed is “FPGA implementation of Encoder and decoder for (15, 11, 3) and (63, 39, 4) Binary BCH code using VHDL with multiple error correction”. The digital logic implementation of binary encoding and decoding of multiple error correcting BCH code of length n=15 and n=63 over GF (24) and GF(26)with irreducible primitive polynomials x4+x+1 and x6+x+1 are organized into n-k linear feedback shift register circuits for encoding. Iterative decoding algorithms are used to find the location of error and decode the message bits at receiver side. Two encoders and decoders are designed using VHDL to encode and decode the triple and four error correcting BCH code corresponding to the coefficient of generated polynomial. For implementation Spartan 3 FPGA processor is used with VHDL and the simulation & synthesis are performed using Xilinx ISE 13.2.