சுருக்கம்

Efficient VLSI Architecture for 2's Complement Based 2-D Discrete Wavelet Transform

Radhe Kant Mishra, Nitin Meena

A 2-D discrete wavelet transform hardware design based on 2’s complement design based architecture is presented in this paper. We have proposed based on arithmetic for low complexity and efficient implementation of 2-D discrete wavelet transform. The 2’s complement design based technique has been applied to reduce the number of full adders. This architecture is suitable for high speed on-line applications, the most important one being image processing. With this architecture the speed of the 2-D discrete wavelet transform is increased. It has 100% hardware utilization efficiency.