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Efficient Implementation of Reconfigurable MIMO Decoder Accelerator Chip

Lakshmi Priya.K

In this paper I present an energy efficient reconfigurable MIMO (Multiple input Multiple output)decoder accelerator hardware architecture. It delivers full programmability across different wireless standards (i.e., WiFi, 3G-long term evolution, and WiMax) as well as different MIMO decoding algorithms (i.e., minimum mean square error, singular value decomposition, and maximum likelihood) with extreme energy efficiency. We propose an Hough transform architecture instead of CORDIC for the Rotation unit in the processing core . The energy efficiency of our MIMO accelerator chip was compared against existing programmable MIMO accelerator, it delivered energy efficiencies that were 5% less than the existing system.