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Design of Multipliers Using Low Power High Speed Logic in CMOS Technologies

Linet. K, Umarani.P, T. Ravi

Designing high speed and low power circuits with CMOS technology have great importance in VLSI circuits. One of the efficient logics among the logic family is the Constant Delay (CD) logic style. In this paper CD logic has been modified and a new logic known as the Low Power High Speed (LP-HS) is proposed. With the help of three changes introduced in the constant delay logic style LP-HS logic is developed which reduces the power delay product. A 4 bit Wallace tree multiplier and Radix 4 multiplier have taken which is then analysed using the constant delay logic as well as LP-HS logic. A comparison has been done on account of the power, delay as well as the power delay product for both the multipliers. The simulations were done using HSPICE tool in 45nm, 32nm, 22nm and 16nm CMOS technologies. The multipliers using LP-HS logic is better in terms of power, delay and power delay product when compared to constant delay logic style.