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DESIGN OF 64 BIT LOW POWER ALU FOR DSP APPLICATIONS

Rajesh Pidugu, P. Mahesh Kannan

The main objective of this project is to design low power 64 bit ALU. Here ALU is designed with the help of multiplexers and full adder. The main component in the ALU is full adder. In CMOS method eight transistor full adder and CMOS based multiplexers are used. In PTL method six transistor full adder and PTL based multiplexers are used. To reduce area, ripple carry adder is used in ALU. Pass transistor logic is used to reduce the number of transistors by eliminating redundant transistors. Number of active devices in PTL logic is less compared to CMOS logic. By using less number of active devices, power consumption is reduced. By reducing area and by using PTL based multiplexers low power ALU is attained. In the implementation of ALU using PTL method, the power and area are reduced to 55% compared to CMOS method.