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Design and Simulation of 64-Bit Carry Select Adder Using Gate Level Architecture for Low Power Applications

Rohit Khare, Sandip Nemade

An efficient VLSI based system has a very high speed operation capability along with low power requirement for performing any operation. The modern systems are required to have very efficient hardware architecture in order to utilize the hardware efficiency to result in best performance. The increasing processor speed and data handling require a high speed circuit to perform the complex calculations. The basic processing operations include addition, multiplication, division, code conversion, encoding-decoding, encryption-decryption, mixing of signal, register-shift, etc. These operations are performed in combination to result in a complex operation. Addition is among the simplest operations. For a data with high length the time taken by the adder to generate output increases in proportion to the length of data. The present work presents the design and simulation of gate level circuit of a 64-bit carry select adder (CSLA) design. The design of CSLA and its simulation test-bench is written using VHDL language. This brief also presents an analysis based on the dynamic power consumption of the field programmable gate array (FPGA) devices in performing the addition operation using the presented design. Xilinx Tool is used in performing the design, simulation and synthesis of the present work.