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Design and Implementation of 8-Bit Vedic Multiplier

Premananda B.S., Samarth S. Pai, Shashank B., Shashank S. Bhat

Currently the speed of the multipliers is limited by the speed of the adders used for partial product addition. In this paper, we proposed an 8-bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) for generating the partial products. The partial product addition in Vedic multiplier is realized using carry-skip technique. An 8-bit multiplier is realized using a 4-bit multiplier and modified ripple carry adders. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay. Simulation of the architecture is carried out using Xilinx ISIM and synthesized using Xilinx XST. Results indicate 13.65% increase in the speed when compared to normal Vedic multiplier.