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DESIGN AND COMPARISON OF RISC PROCESSORS USING DIFFERENT ALU ARCHITECTURES

Sunitha M S, Bharat G Hegde, Deepakakumar N Hegde

Building low-power, high speed systems have been in demand, in recent years, because of the fast growing technologies in mobile communication and computation. Arithmetic and Logic Unit is a core component of almost all computing machines and processors. This work involves the design and comparison of 3 different 16 bit RISC processors based on 3 different ALU architectures. The ALU architectures are differentiated based on consumer requirements, keeping in mind cost, speed and power. Comparisons are done on aspects of area occupied, speed and power consumption. The first ALU design is an economical design, less complex and low power. The second design is a high speed, low power model using Carry Look-Ahead Adders (CLAs) and Vedic multiplier. Extensive parallelism is seen in them. The third design is targeted for low power and compactness and uses Prefix adders and Booth multiplier. The design of the RISC processors also involves the design of memory and development of opcodes which are also included in this work. A typical RISC based program on circular convolution has been implemented on all of these for comparison purposes. Results prove that ALU2 is the fastest and also consumes very less power. It is 15% faster than ALU1 but also occupies 20% more area. ALU3 occupies 30% lesser area than ALU1 and is a low power model. Though moderate in performance, ALU1 is the easiest to design.