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An optimized Mapping of IP Core onto NoC using Multi-Objective Evolutionary Algorithms

N.Janakiraman, P.Mano Arunika , P.Nirmal Kumar

In a System on a Chip (SoC), the communication between the components using network switches is termed as Network on a Chip (NoC). Each interconnection or communication between the components is carried out by the Intellectual Property (IP) block of each component. Mapping of IP core onto NoC is the major NP-hard problem while designing the platform based NoC. To solve this problem, we are using Multi-Objective Evolutionary Algorithms (MOEAs). The IP should be selected to exploit re-usability and to optimize the execution of a given application. Mapping an IP deals with the accurate map of selected IP onto the network platform. The resultant NoC platform will be minimized in the required hardware area, execution time and in power consumption, and the hotspots can also be avoided. Thus providing a custom-cut NoC platform for the application at hand.