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A High Speed and Device Efficient, FPGA Based Squaring Circuit

SHUBHAM MISHRA, SHAILENDRA KUMAR DHAKAD

In this paper a high speed squaring circuit for binary numbers is proposed. The methodology used is inspired from ancient Egyptian method of multiplication. Implementation of this method to binary squaring can increase speed and would improve the device utilization .It was found that the architecture targeted for Xilinx Virtex-4 FPGA( xc4vlx80- 12) used 52 , 4-input LUTS with a combinational delay of 14.972 ns for 32 bit squaring.