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A Greedy Heuristic Algorithm for Flip-Flop Replacement Power Reduction in Digital Integrated Circuits

C.N.Kalaivani, Ayswarya J.J

Power consumed by clocking has taken a major part of the whole design circuit. This paper proposed that reducing the power consumption and area by replacing some flip flops with fewer multi-bit flip-flops without affecting the performance of the original circuit. Various techniques are proposed. First to identify those flip-flops that can be merged. Next a combination table is built to enumerate all possible combinations. Finally, those flip-flops are merged in hierarchical manner. Besides the power reduction minimizing the total wire length is also considered. According to the experimental results clock power can be reduced by 20-30% and the running time can also be reduced