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3D Simulation Study Of Soft Error On Junctionless 6T-SRAM

V.N.Ramakrishnan,R.Srinivasan

As CMOS device is scaling down significantly, the sensitivity of Integrated Circuits (ICs) to Single Event Upset (SEU) radiation increases. As soft errors emerge as reliability threat there is significant interest in the development of various techniques, both at device and circuit level, for SEU hardness in SRAM memories. Junctionless Transistor (JLT) based on 6TSRAM cell is studied in this paper for their SEU or soft error performance using 3D TCAD simulations. The critical dose observed in JLT based 6T-SRAM to flip the cell is given by Linear Energy Transfer (LET) = 0.1 pC/μm. The simulation result analyzes electrical and SEU radiation parameters to study its impact on JLT based 6T-SRAM memory circuits.